Design of All Digital Phase Locked Loop (d-pll) with Fast Acquisition Time
نویسندگان
چکیده
A Digital PLL is designed with improved acquisition time and power efficiency. The implemented D-PLL can operate from 6.54MHz to 105MHz with a power dissipation of is 7.763μW (at 210MHz) with 1.2V supply voltage. The D-PLL is synthesized using cadence RTL compiler in 45nm CMOS process technology.
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تاریخ انتشار 2014